VHDL to Verilog translator
vhd2vl is a VHDL to Verilog translation program. It targets the translation of synthetisable RTL. While far from complete it supports a useful subset of VHDL, sufficient for complex designs.
| Release | Stable | Testing |
|---|---|---|
| Fedora Rawhide | 2.5-23.fc44 | - |
| Fedora 43 | 2.5-22.fc43 | - |
| Fedora 42 | 2.5-21.fc42 | - |
You can contact the maintainers of this package via email at
vhd2vl dash maintainers at fedoraproject dot org.