VHDL to Verilog translator
vhd2vl is a VHDL to Verilog translation program. It targets the translation of synthetisable RTL. While far from complete it supports a useful subset of VHDL, sufficient for complex designs.
Release | Stable | Testing |
---|---|---|
Fedora Rawhide | 2.5-16.fc38 | - |
Fedora 38 | 2.5-16.fc38 | - |
Fedora 37 | 2.5-15.fc37 | - |
You can contact the maintainers of this package via email at
vhd2vl dash maintainers at fedoraproject dot org
.