A fast simulator for synthesizable Verilog
Verilator is the fastest free Verilog HDL simulator. It compiles synthesizable Verilog, plus some PSL, SystemVerilog and Synthesis assertions into C++ or SystemC code. It is designed for large projects where fast simulation performance is of primary concern, and is especially well suited to create executable models of CPUs for embedded software design teams.
Release | Stable | Testing |
---|---|---|
Fedora Rawhide | 5.024-2.fc41 | - |
Fedora 40 | 5.024-2.fc40 | - |
Fedora 39 | 5.022-4.fc39 | - |
Fedora 38 | 4.226-2.fc38 | - |
EPEL 9 | 5.022-3.el9 | - |
EPEL 8 | 4.028-1.el8 | - |
EPEL 7 | 3.922-1.el7 | - |
You can contact the maintainers of this package via email at
verilator dash maintainers at fedoraproject dot org
.