Parse Verilog $readmemh or $readmemb text file
The Verilog Hardware Description Language (HDL) provides a convenient way to load a memory during logic simulation. The $readmemh() and $readmemb() system tasks are used in the HDL source code to import the contents of a text file into a memory variable.
Release | Stable | Testing |
---|---|---|
Fedora Rawhide | 0.05-25.fc40 | - |
Fedora 40 | 0.05-25.fc40 | - |
Fedora 39 | 0.05-23.fc39 | - |
Fedora 38 | 0.05-22.fc38 | - |
You can contact the maintainers of this package via email at
perl-Verilog-Readmem dash maintainers at fedoraproject dot org
.