iverilog
Icarus Verilog is a verilog compiler and simulator
Icarus Verilog is a Verilog compiler that generates a variety of engineering formats, including simulation. It strives to be true to the IEEE-1364 standard.
Releases Overview
| Release | Stable | Testing |
|---|---|---|
| Fedora Rawhide | 13.0-4.fc45 | - |
| Fedora 44 | 13.0-4.fc44 | 13.0-4.fc44 |
| Fedora 43 | 12.0-11.fc43 | - |
| Fedora 42 | 12.0-10.fc42 | - |
| Fedora EPEL 9 | 12.0-12.el9 | - |
| Fedora EPEL 10.3 | 13.0-4.el10_3 | - |
| Fedora EPEL 10.2 | 13.0-4.el10_2 | - |
| Fedora EPEL 10.1 | 13.0-4.el10_1 | - |
File a new bug report »
Package Info
Package Info
- Upstream: https://github.com/steveicarus/iverilog
- License(s): GPL-2.0-only
- Maintainer: filiperosset
You can contact the maintainers of this package via email at
iverilog dash maintainers at fedoraproject dot org.
Sources on Pagure