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Sequential logic synthesis and formal verification

ABC is a growing software system for synthesis and verification of binary sequential logic circuits appearing in synchronous hardware designs. ABC combines scalable logic optimization based on And-Inverter Graphs (AIGs), optimal-delay DAG-based technology mapping for look-up tables and standard cells, and innovative algorithms for sequential synthesis and verification. ABC provides an experimental implementation of these algorithms and a programming environment for building similar applications. Future development will focus on improving the algorithms and making most of the packages stand-alone. This will allow the user to customize ABC for their needs as if it were a toolbox rather than a complete tool.

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EPEL 7 1.01-9.hg20160905.el7 -
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You can contact the maintainers of this package via email at abc dash maintainers at fedoraproject dot org.

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